From f3cafdfecc7a3b7b256c150b5c5452214a5af099 Mon Sep 17 00:00:00 2001
From: Paul Duncan <pabs@pablotron.org>
Date: Sat, 23 Jun 2018 11:27:38 -0400
Subject: add implementation for several missing instructions (still missing
 DAA)

---
 ops.yaml | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 72 insertions(+), 2 deletions(-)

(limited to 'ops.yaml')

diff --git a/ops.yaml b/ops.yaml
index 1a14607..d2faa6d 100644
--- a/ops.yaml
+++ b/ops.yaml
@@ -759,6 +759,8 @@ ops:
         n: "1"
         h: "1"
         c:
+      code: |
+        cpu_wb(ctx, RB_A, cpu_rb(ctx, RB_A) ^ 0xFF);
     - id: JR NC, r8
       hex: 0x30
       cat: "jumps/calls"
@@ -2442,6 +2444,8 @@ ops:
         n: "1"
         h: H
         c: C
+      code: |
+        sbc_rb(ctx, RB_B);
     - id: SBC A, C
       hex: 0x99
       cat: "8-bit math"
@@ -3317,6 +3321,8 @@ ops:
         n: "0"
         h: H
         c: C
+      code: |
+        adc_d8(ctx, old_pc + 1);
     - id: RST 08H
       hex: 0xCF
       cat: "jumps/calls"
@@ -3690,6 +3696,8 @@ ops:
         n: "0"
         h: "1"
         c: "0"
+      code: |
+        and_d8(ctx, old_pc + 1);
     - id: RST 20H
       hex: 0xE7
       cat: "jumps/calls"
@@ -3721,6 +3729,8 @@ ops:
         n: "0"
         h: H
         c: C
+      code: |
+        add_sp_r8(ctx, old_pc + 1);
     - id: JP (HL)
       hex: 0xE9
       cat: "jumps/calls"
@@ -9311,6 +9321,27 @@ templates:
       ));
     }
 
+    static void
+    add_sp_r8(
+      gb_t * const ctx,
+      const uint16_t addr
+    ) {
+      // get old and new value
+      const uint16_t o = cpu_rw(ctx, RW_SP);
+      const int8_t n = (int8_t) mmu_rb(ctx, addr);
+      const uint16_t v = o + n;
+
+      // write value
+      cpu_ww(ctx, RW_SP, v);
+
+      // FIXME: set flags
+      cpu_wf(ctx, F_Z | F_N | F_H | F_C, (
+        ((((o & 0x0F) + (n & 0x0F)) & 0xF0) ? F_H : 0) |
+        ((v & 0x100) ? F_C : 0)
+      ));
+    }
+
+
     static void
     ld_hl_sp_r8(
       gb_t * const ctx,
@@ -9374,6 +9405,28 @@ templates:
       ));
     }
 
+    static void
+    adc_d8(
+      gb_t * const ctx,
+      const uint16_t addr
+    ) {
+      // get old and new value
+      const uint8_t o = cpu_rb(ctx, RB_A),
+                    n = mmu_rb(ctx, addr),
+                    c = FLAG(ctx, C) ? 1 : 0;
+      const uint16_t v = o + n + c;
+
+      // write value
+      cpu_wb(ctx, RB_A, v);
+
+      // set flags
+      cpu_wf(ctx, F_Z | F_N | F_H | F_C, (
+        ((v & 0xFF) ? 0 : F_Z) |
+        ((((o & 0x0F) + (n & 0x0F) + c) & 0xF0) ? F_H : 0) |
+        ((v & 0x100) ? F_C : 0)
+      ));
+    }
+
     static void
     sub_rb(
       gb_t * const ctx,
@@ -9458,7 +9511,7 @@ templates:
         (v ? 0 : F_Z) |
         F_N |
         ((((o & 0x0F) - (n & 0x0F)) & 0xF0) ? F_H : 0) |
-        ((n > o) ? F_C : 0) // FIXME: is this right for sub/sbc?
+        (((((uint16_t) n) + c) > o) ? F_C : 0) // FIXME: is this right for sub/sbc?
       ));
     }
 
@@ -9480,7 +9533,7 @@ templates:
         (v ? 0 : F_Z) |
         F_N |
         ((((o & 0x0F) - (n & 0x0F)) & 0xF0) ? F_H : 0) |
-        ((n > o) ? F_C : 0) // FIXME: is this right for sub/sbc?
+        (((((uint16_t) n) + c) > o) ? F_C : 0) // FIXME: is this right for sub/sbc?
       ));
     }
 
@@ -9519,6 +9572,23 @@ templates:
       ));
     }
 
+    static void
+    and_d8(
+      gb_t * const ctx,
+      const uint16_t addr
+    ) {
+      // get value
+      const uint8_t v = cpu_rb(ctx, RB_A) & mmu_rb(ctx, addr);
+
+      // write value
+      cpu_wb(ctx, RB_A, v);
+
+      // set flags
+      cpu_wf(ctx, F_Z | F_N | F_H | F_C, (
+        (v ? 0 : F_Z)
+      ));
+    }
+
     static void
     xor_rb(
       gb_t * const ctx,
-- 
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