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authorPaul Duncan <pabs@pablotron.org>2018-06-19 21:28:05 -0400
committerPaul Duncan <pabs@pablotron.org>2018-06-19 21:28:05 -0400
commit45ba14fcbeb5f7db44e7cb60cae075c901c61dfd (patch)
tree953648fe16cbb71c453d7f8ec01be97256c10932
parentf28380cc5c2c82da4120035009ae6e368cdbae16 (diff)
downloadgb-c-45ba14fcbeb5f7db44e7cb60cae075c901c61dfd.tar.bz2
gb-c-45ba14fcbeb5f7db44e7cb60cae075c901c61dfd.zip
simplify mmu_{wb,rb}(): add {rom,ram}_{wb,rb}()
-rw-r--r--ops.yaml120
1 files changed, 95 insertions, 25 deletions
diff --git a/ops.yaml b/ops.yaml
index 27950ac..ac4b0a7 100644
--- a/ops.yaml
+++ b/ops.yaml
@@ -7912,7 +7912,7 @@ templates:
}
static uint8_t
- mmu_rb(
+ rom_rb(
gb_t * const ctx,
const uint16_t addr
) {
@@ -7929,14 +7929,11 @@ templates:
// return ROM0 (16k, always mapped)
return ctx->mmu.rom[addr];
-
- break;
case 0x1000:
case 0x2000:
case 0x3000:
// return ROM0 (16k, always mapped)
return ctx->mmu.rom[addr];
- break;
case 0x4000:
case 0x5000:
case 0x6000:
@@ -7944,12 +7941,22 @@ templates:
// return ROM1 (16k, banked)
// TODO:
return ctx->mmu.rom[addr];
- break;
+ default:
+ // never reached
+ return 0;
+ }
+ }
+
+ static uint8_t
+ ram_rb(
+ gb_t * const ctx,
+ const uint16_t addr
+ ) {
+ switch (addr & 0xF000) {
case 0x8000:
case 0x9000:
// return vram (8k)
return ctx->mmu.vram[addr & 0x1FFF];
- break;
case 0xA000:
case 0xB000:
if (ctx->mmu.eram) {
@@ -7959,17 +7966,43 @@ templates:
// FIXME: what do we do with no eram?
return 0;
}
-
- break;
case 0xC000:
case 0xD000:
// working ram (8k)
return ctx->mmu.ram[addr & 0x1FFF];
- break;
case 0xE000:
+ case 0xF000:
// working ram (shadow)
return ctx->mmu.ram[addr & 0x1FFF];
- break;
+ default:
+ // never reached
+ return 0;
+ }
+ }
+
+ static uint8_t
+ mmu_rb(
+ gb_t * const ctx,
+ const uint16_t addr
+ ) {
+ switch (addr & 0xF000) {
+ case 0x0000:
+ case 0x1000:
+ case 0x2000:
+ case 0x3000:
+ case 0x4000:
+ case 0x5000:
+ case 0x6000:
+ case 0x7000:
+ return rom_rb(ctx, addr);
+ case 0x8000:
+ case 0x9000:
+ case 0xA000:
+ case 0xB000:
+ case 0xC000:
+ case 0xD000:
+ case 0xE000:
+ return ram_rb(ctx, addr);
case 0xF000:
switch (addr & 0x0F00) {
case 0x0E00:
@@ -7980,8 +8013,6 @@ templates:
// rest of page reads as zero
return 0;
}
-
- break;
case 0x0F00:
if (addr == PORT_IE || addr < 0xFF80) {
// io port
@@ -7990,14 +8021,10 @@ templates:
// zero page
return ctx->mmu.zram[addr & 0x7F];
}
-
- break;
default:
- // working ram (shadow)
- return ctx->mmu.ram[addr & 0x1FFF];
+ // working ram (<0xFE00, 8k, shadow)
+ return ram_rb(ctx, addr);
}
-
- break;
default:
// never reached
return 0;
@@ -8005,11 +8032,14 @@ templates:
}
static void
- mmu_wb(
+ rom_wb(
gb_t * const ctx,
const uint16_t addr,
const uint8_t val
) {
+ // TODO: implement banking
+ UNUSED(val);
+
switch (addr & 0xF000) {
case 0x0000:
// bios memory (maybe)
@@ -8038,6 +8068,19 @@ templates:
// ROM1 (16k, banked)
// return ctx->mmu.rom[addr];
break;
+ default:
+ // never reached
+ break;
+ }
+ }
+
+ static void
+ ram_wb(
+ gb_t * const ctx,
+ const uint16_t addr,
+ const uint8_t val
+ ) {
+ switch (addr & 0xF000) {
case 0x8000:
case 0x9000:
// vram (8k)
@@ -8054,14 +8097,41 @@ templates:
break;
case 0xC000:
case 0xD000:
- // working ram (8k)
+ case 0xE000:
+ case 0xF000:
+ // working ram (8k, shadow)
ctx->mmu.ram[addr & 0x1FFF] = val;
+ default:
+ // never reached
+ break;
+ }
+ }
+ static void
+ mmu_wb(
+ gb_t * const ctx,
+ const uint16_t addr,
+ const uint8_t val
+ ) {
+ switch (addr & 0xF000) {
+ case 0x0000:
+ case 0x1000:
+ case 0x2000:
+ case 0x3000:
+ case 0x4000:
+ case 0x5000:
+ case 0x6000:
+ case 0x7000:
+ rom_wb(ctx, addr, val);
break;
+ case 0x8000:
+ case 0x9000:
+ case 0xA000:
+ case 0xB000:
+ case 0xC000:
+ case 0xD000:
case 0xE000:
- // working ram (shadow)
- ctx->mmu.ram[addr & 0x1FFF] = val;
-
+ ram_wb(ctx, addr, val);
break;
case 0xF000:
switch (addr & 0x0F00) {
@@ -8083,8 +8153,8 @@ templates:
break;
default:
- // working ram (shadow)
- ctx->mmu.ram[addr & 0x1FFF] = val;
+ // working ram (<0xFE00, 8k, shadow)
+ ram_wb(ctx, addr, val);
}
}
}