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-rw-r--r--ops.yaml80
1 files changed, 58 insertions, 22 deletions
diff --git a/ops.yaml b/ops.yaml
index f08a64a..158b6df 100644
--- a/ops.yaml
+++ b/ops.yaml
@@ -7517,8 +7517,9 @@ ops:
set_rb(ctx, RB_A, 7);
templates:
main: |
- #include <stdint.h>
- #include <stdbool.h>
+ #include <string.h> // memset()
+ #include <stdint.h> // uint8_t ,etc
+ #include <stdbool.h> // bool
#include "gb.h"
#define UNUSED(a) ((void) (a))
@@ -7686,6 +7687,10 @@ templates:
) {
switch (addr & 0xF000) {
case 0x0000:
+ case 0x1000:
+ case 0x2000:
+ case 0x3000:
+ #if 0
// bios memory (maybe)
if (ctx->mmu.in_bios) {
if (addr < 0x100) {
@@ -7694,12 +7699,8 @@ templates:
ctx->mmu.in_bios = false;
}
}
+ #endif /* 0 */
- // return ROM0 (16k, always mapped)
- return ctx->mmu.rom[addr];
- case 0x1000:
- case 0x2000:
- case 0x3000:
// ROM0 (16k, always mapped)
return ctx->mmu.rom[addr];
case 0x4000:
@@ -7817,6 +7818,10 @@ templates:
) {
switch (addr & 0xF000) {
case 0x0000:
+ case 0x1000:
+ case 0x2000:
+ case 0x3000:
+ #if 0
// bios memory (maybe)
if (ctx->mmu.in_bios) {
if (addr < 0x100) {
@@ -7825,12 +7830,8 @@ templates:
ctx->mmu.in_bios = false;
}
}
+ #endif /* 0 */
- // return ROM0 (16k, always mapped)
- return ctx->mmu.rom[addr];
- case 0x1000:
- case 0x2000:
- case 0x3000:
// ROM0 (16k, always mapped)
return ctx->mmu.rom[addr];
case 0x4000:
@@ -9609,19 +9610,15 @@ templates:
void
gb_set_buttons(
gb_t * const ctx,
- const uint8_t btn,
- const bool set
+ const uint8_t btns
) {
- if (set) {
+ if (ctx->mmu.btns != btns) {
// set buttons
- ctx->mmu.btns |= btn;
- } else {
- // clear buttons
- ctx->mmu.btns &= ~btn;
- }
+ ctx->mmu.btns = btns;
- // trigger p1 interrupt
- mmu_wb(ctx, PORT_IF, mmu_rb(ctx, PORT_IF) & (1 << 4));
+ // trigger p1 interrupt
+ mmu_wb(ctx, PORT_IF, mmu_rb(ctx, PORT_IF) & (1 << 4));
+ }
}
void
@@ -9634,3 +9631,42 @@ templates:
gb_step(ctx);
}
}
+
+ const uint8_t *
+ gb_get_rgb_frame(
+ const gb_t * const ctx
+ ) {
+ return ctx->gpu.rgb;
+ }
+
+ static void
+ cpu_init(
+ gb_t * const ctx
+ ) {
+ // set cpu state
+ ctx->cpu.state = STATE_RUN;
+
+ // init cpu registers
+ // (src: TCAGBD.pdf, 3.2)
+ ctx->cpu.rs[RW_AF] = 0x01B0;
+ ctx->cpu.rs[RW_BC] = 0x0013;
+ ctx->cpu.rs[RW_DE] = 0x00D8;
+ ctx->cpu.rs[RW_HL] = 0x014D;
+ ctx->cpu.rs[RW_SP] = 0xFFFE;
+ ctx->cpu.rs[RW_PC] = 0x0100;
+ }
+
+ void gb_init(
+ gb_t * const ctx,
+ const uint8_t * const rom,
+ const uint32_t rom_size
+ ) {
+ // clear context
+ memset(ctx, 0, sizeof(gb_t));
+
+ cpu_init(ctx);
+
+ // init mmu
+ ctx->mmu.rom = rom;
+ ctx->mmu.rom_size = rom_size;
+ }