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authorPaul Duncan <pabs@pablotron.org>2024-05-29 22:05:03 -0400
committerPaul Duncan <pabs@pablotron.org>2024-05-29 22:05:03 -0400
commit161a4f1bedd29fa19896c44295267bbf89dd7afa (patch)
tree48e8893e7230ec99644b21062cd1e3273caaf21c /README.md
parentf3e10c9418998efdcfda829fd43d08c875e7e528 (diff)
downloadsha3-main.tar.bz2
sha3-main.zip
README.md: add avx2 to "Backends"HEADmain
Diffstat (limited to 'README.md')
-rw-r--r--README.md8
1 files changed, 6 insertions, 2 deletions
diff --git a/README.md b/README.md
index c221e77..6ab3da9 100644
--- a/README.md
+++ b/README.md
@@ -211,6 +211,8 @@ The available backends are:
- Scalar (`BACKEND=1`): Default if no faster backend is available.
- [AVX-512][] (`BACKEND=2`): [AVX-512][] acceleration. Selected by
default if [AVX-512][] is supported.
+- [AVX2][] (`BACKEND=6`): [AVX2][] acceleration. Currently slower than
+ the scalar backend and not enabled by default.
- [Neon][] (`BACKEND=3`): ARM [Neon][] acceleration. Currently slower
than the scalar backend on ARM CPUs and not enabled by default.
@@ -225,8 +227,8 @@ A minimal [libcpucycles][]-based benchmarking tool is available in
byte (cpb)][cpb] for a variety of message lengths, then prints a table
of results to standard output in [CSV][] format.
-The results from running `bench` on a couple of my systems are available
-in the tables below.
+`bench` results from several of my systems are shown in the tables
+below.
### Lenovo ThinkPad X1 Carbon, 6th Gen (i7-1185G7, AVX-512 Backend)
@@ -352,3 +354,5 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
"Observed CPU cycles divided by the number of input bytes."
[median]: https://en.wikipedia.org/wiki/Median
"Median"
+[avx2]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2
+ "Advanced Vector Extensions 2: 256-bit SIMD vector instruction set"